Recently, demands for reduction in size, in thickness and in weight of portable electronic equipment such as digital video cameras, digital portable phones, and laptop personal computers have been increased. In order to respond to these demands, about 70% reduction in size has been realized in three years in semiconductor devices such as a recent VLSI or the like. However, it cannot be said that this is a sufficient amount, and that improvement in the part packaging density on a packaged substrate is cited as an important problem. Accordingly, research and development into this problem have been conducted.
As a conventional semiconductor package, for example, a Through Hall Mount Device (THD) package and a Surface Mount Device (SMD) package have been adopted. In the through hall mount device package, mounting is performed by inserting a lead wire into a through hall provided to a printed board. As an example for it, a Dual Inline Package (DIP), a Pin Grid Array (PGA) and the like can be cited. In the surface mount type package, mounting is conducted by soldering a lead wire on the surface of the substrate. As this example, a Quad Flat Package (QFP), a Tape Carrier Package (TCP), a Ball Grid Array (BGA), a Chip Size Package (CSP), and the like can be cited.
As for the BGA or the CSP, a semiconductor integrated circuit (IC) chip is attached and fixed on one surface of a printed board. On the other surface of the printed board, a plurality of external connection terminals made of solder balls are attached. A plurality of electrodes of the IC chip are led-through to the external connection terminals. FIG. 9 is a perspective view showing a conventional BGA package, and FIG. 10 is a cross sectional view showing the conventional BGA package.
In the conventional BGA package, an IC chip (semiconductor integrated circuit) 105 is mounted on one surface of a printed board 101 for an interposer. As an insulating layer composing the printed board 101, a glass epoxy resin layer, a polyimide layer, or the like are used, for example. In addition, on the other surface of the printed board 101, a plurality of external connection terminals 108 made of solder balls are provided. Bonding wires 106 are connected to a plurality of electrodes 110 provided on the upper surface of the IC chip 105, and the other ends of the bonding wires 106 are connected to lands 102 provided to the printed board 101. A conductive layer (not shown) is provided in the printed board 101. The lands 102 are connected to the external connection terminals 108 via the conductive layer. Then, a package resin 107 to cover the IC chip 105 and so on is formed. Thus, a packaged semiconductor device is composed.
When the semiconductor device is installed on a mother printed board 151, as shown in FIG. 11, after each external connection terminal 108 of the semiconductor device is abutted on a printed board terminal 152 provided to the mother printed board 151, the lower portions of the respective external connection terminals 108 are melted and welded to the printed board terminals 152 by reflowing.
When such an installation is performed, however, as shown in FIG. 12, the printed board 101 for the interposer sometimes bends backward due to the thermal stress caused by the reflowing. As a result, the IC chip 105 which is inside the semiconductor device also bends. When a piezoelectric device such as a ferroelectric capacitor or the like composing a ferroelectric memory is contained in the IC chip 105, since a compressive stress or a tensile stress is applied on the piezoelectric device, normal operations are impossible. In particular, when a ferroelectric memory is provided, data storage functions may be lost, data readout becomes disabled, or malfunctions may occur.
Furthermore, even in a chip which shows no problems at the time of reflowing, moisture may penetrate into the inside the IC chip with extended use. This results in expansion and distortion of the chip, and may cause malfunctions as described above.
Patent Document 1: Japanese Patent Application Laid-open No. 2001-60638
Patent Document 2: Japanese Patent Application Laid-open No. 2001-156095
Patent Document 3: Japanese Patent Application Laid-open No. 2001-85458
Patent Document 4: Japanese Patent Application Laid-open No. Hei 7-45735